For years, system-on-chip (SoC) design has been the path to higher integration. This path has been somewhat guided by the industry’s need for smaller and faster devices that maintain superior power efficiency. While equipping a single die with more functionality has helped meet those demands and simplified system design, as things get more complex and process nodes become more specialized, that approach is showing its limitations.
Chiplets offer a different path forward, breaking monolithic designs into modular building blocks that can be combined within a single package. These integrated devices have evolved from discrete integrated circuits (ICs) and simpler application-specific integrated circuits (ASICs) or application-specific standard products (ASSPs) toward increasingly complex SoCs. ASICs, ASSPs, and SoCs all have one thing in common: They are fabricated on a single wafer using a single semiconductor process.
This approach offered clear benefits, such as reduced size and faster time to market, but it also introduced new drawbacks that have become more pronounced as technology has advanced. The process of stitching together different pieces of intellectual property (IP) into a single entity is complex, and this complexity increases as larger, more complex functions are incorporated into SoCs. There is no guarantee that the desired IP block will be available and optimized for the specified fabrication node, which can delay optimization or require a compromise to choose a different IP block to keep the project on schedule. Since the ICs are fabricated using a specific manufacturing process on a single node, if a developer were to integrate an IP block that required a different process (e.g., a power circuit), the whole chip would have to be built on the larger node. This would hinder the performance of the digital sections and be much less efficient.