We interacted with the Founder and CEO of Maven Silicon, Mr. P R Sivakumar, to understand his vision and entrepreneurial journey. We are delighted to share his vision of democratizing chip design by empowering the next generation of VLSI and Embedded Systems engineers with RISC-V expertise, and his perspectives on building a global semiconductor talent ecosystem.
Design & Reuse: Share your entrepreneurial journey at Maven Silicon and your long-term vision to build a talent ecosystem for the semiconductor industry.
Sivakumar: I have worked in various fields, including electrical engineering, academia, and semiconductors, for over 28 years. Before founding Maven Silicon, I was part of the EDA industry and served as a Verification Consultant for leading EDA companies such as Synopsys, Cadence, and Siemens EDA. At Maven, we started our journey in 2010 as a VLSI finishing school by introducing career-oriented VLSI courses specialized in Design Verification for new college graduates. In our journey, we have produced more than 6000 chip designers in India who are working in the Indian and global semiconductor industry across various startups and MNCs – IDMs, EDA, fabless chipmakers, IP, and design services companies.
In this incredible journey, we have been collaborating with various global organizations, such as RISC-V International, Altera, ARM, and SEMI, as their global training partner to build and expand our expertise into other essential domains beyond ASIC – CPUs, FPGA, Embedded Systems Programming, and Fabrication. It helped us emerge as a Centre of Excellence in Semiconductors to serve industry and academia. Synopsys, Cadence and Siemens EDA are our EDA partners. As a founder, I am proud to see Maven Silicon as a preferred semiconductor training partner of global chipmakers in India, upskilling their workforce worldwide.
Our long-term vision is to produce highly knowledgeable and skilled VLSI and Embedded engineers who can create the next generation of semiconductor systems that demand cutting-edge technologies and methodologies – AI-powered VLSI and Embedded Systems Design, SoCs with heterogeneous computing, Chiplets, Advanced Packaging, etc.
Design & Reuse: Why did you collaborate with RISC-V International as a Global RISC-V Training Partner? Explain your journey with RISC-V International.
Sivakumar: At Maven Silicon, we wanted to build our domain expertise in processors and CPU ISAs because understanding one good processor, especially a Reduced Instruction Set Computer like RISC-V, is essential for young engineers who want to build a long-term career in the semiconductor field – VLSI and Embedded Systems.
RISC-V, as an open ISA, was a golden opportunity for us to explore the complete ISA and understand everything related to systems – Bare-metal embedded systems, OS-managed SoCs, and Hypervisor-managed server chips that demand all kinds of features such as system booting and initialization, OS address translation schemes and MMUs, traps, exceptions and interrupts, memory and I/O management, virtualization, device drivers, toolchains, software debugging, etc.
Today, RISC-V ISA is a part of our VLSI and ESD course curriculum, and every VLSI and Embedded engineer at Maven Silicon begins their journey by learning RISC-V ISA as an alphabet of the semiconductor systems language.
Beyond learning the instruction set, we want engineers to understand the ISA features through various real-time examples – physical memory protection for secure bare-metal embedded systems, memory address space frameworks for 32-bit and 64-bit SoCs, running firmware directly in the physical address space without an MMU even in OS-managed systems, system booting through assembly code and seamless transition into OS kernel initialization and high-level software execution, traps, trap handlers and trap delegation, CPU pipeline design, software debugging, etc.
RISC-V International, as a non-profit organization, supports all kinds of organizations – chipmakers, the EDA industry, and academia – with equal importance. Regular access to their well-updated ISA specifications, open-source designs/examples/software and toolchains, newsletters, and RISC-V Summit technical session videos on YouTube are always good references. It truly reflects the culture of openness.
Supporting the next-generation engineers with the vision of democratizing chip design through imparting open RISC-V ISA is important for us and is a driving force for our long-term, meaningful journey as a Semicon-COE at Maven Silicon. We are a proud RISC-V Global Training Partner.
Design & Reuse: What are the biggest gaps today between academia and industry in semiconductors? How do you address those gaps?
Sivakumar: In this AI era, engineers need systems thinking beyond doing their jobs as skilled coders. Engineers’ careers have been highly driven by the evolution of programming languages, design methodologies, and EDA/toolchains.
In VLSI, we use HDLs such as Verilog HDL and VHDL for RTL design, HVL SystemVerilog and Universal Verification Methodology for design verification, and various methodologies and EDA tools for Design for Testing, Analog Design, and Physical Design.
Now, with AI tools such as copilots and Agentic AI, programming work such as RTL/testbench coding, Python, C, TCL/TK programming, and EDA flow implementation could be highly automated. But it needs engineers’ due diligence and involvement in implementing the design flow and producing bug-free silicon without expensive respins. It is the same for embedded system programming in terms of creating embedded software and programming bug-free hardware systems.
As I explained, at Maven Silicon, every VLSI and Embedded engineer begins their journey by learning how we build various hardware systems – Bare-metal embedded systems, OS-managed SoCs, and Hypervisor-managed server chips. It helps engineers understand the big picture: the complete design cycle – how we implement electronic systems by creating SoCs, the software stack – firmware, OS, & applications, PCBs – chipsets, and post-silicon validation, etc.
But beyond understanding the big picture, engineers need to be specialized in a specific domain – VLSI: Design, DV, DFT, AMS, PD, etc., and ESD: Firmware, Device Drivers, Bare-metal/RTOS, OS, Applications, etc. Depending on their preference, we train them extensively in a specific domain and make them project-ready.
For example, a DV engineer who uses firmware C testcases to configure the SoC before running any UVM testcase will never understand this verification process without knowing CPUs and systems. If AI tools can generate such SoC testcases, then we need DV engineers as domain experts who can collaborate with designers and architects at the verification planning level to verify the systems. Can they speak their language – systems language – beyond writing testcases and using EDA tools?
Design & Reuse: How are you planning to build a strong RISC-V engineering community spanning IC design, embedded firmware, and operating systems?
Sivakumar: We are a community-driven organization. As a self-funded company, it is the only powerful way we can continue our long-term journey meaningfully, forever, without losing our relevance in the global semiconductor ecosystem.
At present, we are empowered by our alumni community. The top 10% of our alumni, more than 500 engineers, are today working as tech leads and project managers in the global semiconductor industry. They are part of our advisory board, defining new curricula and updating our existing curricula and pedagogy.
We have various semiconductor training programs – VLSI and ESD courses for new college graduates, working professionals, corporates, and academia.
Since our association with RISC-V International as their training partner, we have produced thousands of VLSI engineers with RISC-V expertise. Today, they are working in the semiconductor industry across various companies – startups and MNCs. Everyone might not be working on RISC-V CPUs/SoCs, but with RISC-V expertise, they can understand any other proprietary CPUs and SoCs and execute their projects.
Now, with this success, we have introduced our embedded courses with RISC-V ISA as a trailblazer in the embedded software ecosystem, which is typically dominated by a few proprietary CPU giants. It helps us build a strong VLSI and Embedded engineers community with RISC-V expertise.
India is ambitiously gearing up with semiconductor fabs, ATMPs, OSATs, and VLSI fabless design startups, with good government funding support under the Indian Semiconductor Mission scheme, to build a strong semiconductor ecosystem. Various organizations such as C-DAC and IIT Madras have designed their own RISC-V processors and created a good RISC-V IP design ecosystem for fabless design startups in India. It inspires many Indian design startups to use RISC-V ISA for their IPs and SoCs.
I am also in the process of making my other venture Aceic Design Technologies into an automotive chipmaker. We want to collaborate with Tier-1 automotive suppliers and OEMs to design RISC-V SoCs for their zonal architecture, especially to help Indian OEMs evolve and grow in the transformative journey – MCUs to Zonal Architecture to SDV. Having built good RISC-V domain expertise and a talent ecosystem at Maven Silicon gives me immense confidence to hire sound VLSI and Embedded engineers and build Aceic as a chipmaker.
Semiconductor design talent is equally important as good funding support for the successful launch and long-term growth of any chipmaker startup.
Design & Reuse: What kind of partnerships (industry, academia, and open source) are critical to sustain such a community?
Sivakumar: We need a mature software ecosystem for any RISC-V-based fabless design startup to succeed.
RISC-V ISA is evolving powerfully as an industry-standard open ISA, supporting heterogeneous computing architectures for next-generation SoCs that use all kinds of processors, including CPUs, GPUs, Image Processors, AI accelerators, etc.
The success of this evolution depends on the support from global chipmakers, fabless IP companies, AI startups, EDA, and embedded software companies in terms of adopting RISC-V ISA and building a good global hardware and software ecosystem.
It demands tech visionary leaders across industry, academia, and open-source/non-profit organizations who believe in democratizing chip design through open ISA.
Design & Reuse: How do you envision the RISC-V talent community developed by Maven Silicon evolving over the next 5 years across SoC design and Embedded Systems programming?
Sivakumar: The Indian semiconductor industry is dominated and driven primarily by design and support services businesses. In VLSI, most of them are DV and PD-skilled engineers who work for global chipmakers. They may be highly skilled in their domain, but their exposure to the complete product development cycle – Specification to Silicon Tapeout to Post-silicon Validation – is limited.
In this AI era, their job roles and responsibilities will change/evolve, and some jobs will merge/disappear due to AI automation – chip design using AI-powered EDA. In order to address their skill gaps and upskill, we now offer various RISC-V-powered Executive PG degree and certification courses under premier institutes such as iHUB – IIT Roorkee, IIT Madras – Pravartak, and NIELIT for working professionals, beyond our B2B-corporate bootcamp courses. It helps us prepare them for their long-term careers in the AI-driven semiconductor industry. I am delighted to inform you that we will be offering more such online executive courses through the SEMI University online platform globally soon.
We branded our executive courses as RISC-V-powered executive courses because the entire course curriculum is based on the RISC-V Open ISA. It helps working professionals learn all aspects of systems/SoCs – Bare-metal embedded 32/64-bit microcontrollers and OS-managed 64-bit SoCs – and explore the complete product development cycle, from Specification to final product.
I believe this initiative helps us build a semiconductor talent pipeline – next-generation architects, tech leads, engineering managers, product marketing experts, and entrepreneurs for the new semiconductor design startups in India and globally.
Design & Reuse: What are the key technical skills engineers must develop to contribute meaningfully to RISC-V SoC design?
Siva: As I explained previously, understanding the complete RISC-V ISA features through various real-time examples is foundational to SoC design – designing simple bare-metal MCUs using RV32EC, designing OS-based 64-bit SoCs using RV64GC, designing AI accelerators using specific extensions, understanding how the RISC-V Vector extension can be used to accelerate AI, DSP and data-parallel workloads, and how Scalar Crypto and Vector Crypto extensions can be used to build hardware support for security and cybersecurity applications, understanding privilege modes and CSR architecture, physical memory protection features for secure bare-metal embedded MCUs, understanding the memory address space framework for 32-bit and 64-bit SoCs, physical vs. virtual address spaces, MMU design, running firmware directly in the 32-bit physical address space without an MMU even for OS-managed systems, system booting through assembly code and seamless transition into OS kernel initialization and high-level software execution, traps – trap handlers and trap delegation, CPU pipeline design, software debugging, etc.
Exploring the open-source RISC-V operating system xv6 kernel source code will help chip designers understand the purpose and role of registers – RISC-V ISA unprivileged and privileged architectures and features.
In addition to a deep understanding of ISA, engineers must learn an on-chip bus interconnect, such as AMBA – AXI, AHB, and APB, and external interface protocols such as SPI, UART, I2C, GPIO, USB, etc.
Building good expertise in SoC controller design, IP, and subsystem integration is essential.
Exploring the complete product development cycle on a real-time project – Specification to Silicon Tapeout – involving all the domains/methodologies such as RTL design, DV, Synthesis, DFT, PD, Silicon Tapeout, Packaging, PCB – ASIC Prototyping, and Post-silicon software validation will make them a strong candidate for SoC design and help them emerge as architects.
Design & Reuse: What are the key technical skills engineers must develop to contribute meaningfully to Embedded Systems Programming?
Sivakumar: I believe the starting point is a strong understanding of the complete RISC-V ISA and its programming model through real implementation examples like developing bare-metal firmware for RV32EC-based embedded systems, developing 64-bit applications on RV64GC-based SoCs, understanding registers, CSRs, privilege modes, physical and virtual address spaces, memory-mapped I/O, atomic operations, memory protection, and how C and assembly interact with the processor.
The Engineers should also clearly understand the RISC-V profiles, particularly RVB23 for embedded and edge-oriented systems and RVA23 for application processors and OS-based systems. This gives them a much better perspective on how the architecture evolves from resource-constrained embedded systems to powerful application processors.
A good embedded engineer should know what happens from reset to running firmware – startup code, linker scripts, stack initialization, BSP (Board Support Package) development, memory maps, memory-mapped I/O, bootloaders and peripheral drivers. Writing these pieces themselves, rather than always depending on a vendor SDK (Software Development Kit), develops the right level of understanding.
Interrupts and traps are another area that needs much deeper attention. Engineers should understand exceptions, interrupt handling, trap delegation, CSRs, context saving, and both direct and vectored trap handling, along with the role of CLINT (Core-local Interrupt Controller), PLIC (Platform-Level Interrupt Controller) and the newer RISC-V Advanced Interrupt Architecture (AIA). These become fundamental when moving from simple firmware to RTOS and OS-based systems.
For embedded programming, strong C and assembly skills, along with RTOS concepts and interfaces such as SPI, UART, I2C, GPIO, timers, DMA and watchdogs, are essential. Engineers should be able to look at a datasheet or reference manual, understand the registers and write the driver themselves.
Then I would move to the OS side. Studying a simple RISC-V OS such as xv6 is a very good way to understand virtual memory, page tables, system calls, processes, traps and device drivers. From there, engineers should learn how to build and customise Linux for RISC-V using Yocto or Buildroot, including kernel configuration, device trees, root filesystems, drivers and applications for different RVA23-based SoCs.
And I think there is one area that can really differentiate engineers in the coming years: virtualization. Understanding the RISC-V Hypervisor architecture and eventually being able to build a Type-1 hypervisor for a RISC-V application processor brings together CPU architecture, memory management, interrupts, isolation, device virtualization and operating-system knowledge. This is particularly relevant to servers and automotive systems, where hypervisors are used to consolidate multiple workloads while isolating safety-critical functions. Platforms such as QNX have already demonstrated the importance of this approach in automotive systems.
This is also an area where RISC-V still has significant room for innovation compared with the much more mature virtualization ecosystems around ARM and x86. Engineers who can work at this level, and actually build and debug such systems, can therefore bring a very different kind of value to the RISC-V ecosystem.
Finally, engineers should develop the ability to debug across the hardware-software boundary. The real skill is not just writing firmware or Linux code, but understanding why the complete system behaves the way it does.
For me, the journey is from RV32EC bare-metal programming to RVB23 embedded systems, then RV64GC and RVA23 application processors, Linux, and finally virtualization and hypervisors. Once an engineer can move across these layers, they stop being just a firmware programmer and start developing the system-level thinking needed to become a RISC-V systems engineer or architect.