ARM last week announced the first phase of its AMBA 4 specification, and Cadence simultaneously released Incisive verification IP (VIP) for the e language and SystemVerilog. So why is ARM releasing AMBA 4, what's in the two phases, and what's in the VIP? To get a closer look at what's in the AMBA 4 specification I talked to Keith Clarke, vice president and general manager of Fabric IP at ARM's Processor Division.
The widely-used AMBA 3 spec has been around since 2003, and it was time for an upgrade, Keith said. He noted that AMBA 4 was developed in conjunction with some 35 partners, including Cadence. A big motivation, he said, is the increase in performance of processor cores, as well as the ability to place multiple cores on SoCs and to support many different functions on a chip.
Additionally, the phase one release that was disclosed last week adds new support for FPGAs. Phase one includes the AXI4, AXI4-Lite, and AXI-Stream protocols. The phase two release, which will be disclosed later this year, will bring in features that will help users develop and program multicore SoCs.
Pete Heller, product line manager for VIP at Cadence, said he is "definitely seeing interest" among the customer base for AMBA 4. "The traditional mobile guys are currently planning their roadmaps for it," Pete said. What's attracting customers, he said, is increased performance, along with a hoped-for power savings.
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