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I am happy to write that Nusym’s pioneering coverage convergence technology is now part of Synopsys.

Over the years, I’ve seen the “long pole” in verification schedules shift based on the evolution of verification technologies and chip architectures.  A few years ago one of the long poles was writing tests – it was nearly impossible to think of and write the tests required to verify all of the likely operational scenarios for a complex design.  Fortunately constrained-random verification with SystemVerilog emerged and made it much easier to automatically generate the thousands of tests needed.  Today it is not uncommon to go from 0% to 80% coverage in just a few days after the SystemVerilog testbench is up & running.

What about the remaining 20%?

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