TowerJazz, the specialty semiconductor foundry created by the merger of Tower Semiconductor and Jazz Semiconductor in 2008, has announced that it has licensed its “Y-Flash” MTP (multiple-times programmable) CMOS memory IP to an unnamed, “leading” digital foundry. TowerJazz’s Y-Flash IP creates a Flash memory cell with standard CMOS processing. In other words, the Y-Flash memory cell has only one gate and it’s a floating gate so there’s no cost adder required to place a Y-Flash memory array on a standard CMOS ASSP, ASIC, or SOC. Conventional Flash memory cells have a floating gate buried beneath a conventional FET gate and fabrication of Flash memory cells may require the use of ten or more additional masks to create that extra gate and the insulation oxides needed to isolate the floating gate from the rest of the FET. TowerJazz’s Y-Flash cell design requires no additional mask steps, or can be performance-enhanced with two additional but "non-critical" mask steps. TowerJazz’s press release says that Y-Flash IP is well suited for memory arrays as small as one bit and as large as 256 kbits, although a technical paper on the TowerJazz site sets the practical upper limit for Y-Flash memory-array capacity at 1 Mbit.