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What are the "gotchas" as design teams move to 40 nm process nodes and below? The best way to find out is to hear from someone who's been there. At Management Day at the recent Design Automation Conference, Jitendra Khare, director of central engineering at AppliedMicro, presented the most comprehensive and informative list I've seen of the challenges that emerge as SoCs move to 40 nm.

While Management Day looked at both the technical and business challenges of complex SoCs, Khare's presentation, in a paper session I moderated, stayed on the technical side. (I previously blogged about a Management Day panel on which Khare and four other presenters appeared). Management Day was sponsored by Cadence.

Khare opened his presentation by talking about trends that are driving SoCs to lower process nodes, including multiple embedded cores, complex interfaces, smart power management, and cost concerns. The need to support a variety of applications with low-cost hardware is a key overall driving force.

But there are some things that "need to be done differently for 40 nm SoCs," as Khare said. Here are some of the challenges he cited.

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