Industry Expert Blogs

Earlier this week Cadence announced that it worked with ARM to develop an implementation methodology for the recently announced, high-end ARM Cortex-A15 processor core, code-named Eagle. The ARM Cortex-A15 processor core has an expanded 40-bit (1Tbyte) memory address space (called Large Physical Address Extensions, LPAE), parity and ECC built into the processor’s cache controllers for both the L1 (32Kbytes of instruction and 32Kbytes of data per processor core) and L2 (maximum size = 4 Mbytes, shared among as many as four processor cores) caches, an AMBA 4 AXI Coherency Extensions (ACE) interface port, and hardware support for multicore designs and virtualization.  According to the specification page, the ARM Cortex-A15 processor supports coherent multiprocessing using as many as four closely connected CPUs and supports multiple SMP (symmetric multiprocessing) clusters connected via the AMBA 4 interconnect fabric. The processor core’s virtualization capabilities involve “hardware support for data management and arbitration, whereby multiple software environments and their applications are able to simultaneously access the system capabilities” according to the online specification page. These are truly the specs of an apps-driven processor core.

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