In my last blog I talked about debugging a design within an FPGA. This week I want to turn the tables completely and talk about using FPGAs as a way to verify ASICs. FPGAS can emulate a design at speeds close to their actual operating frequencies, enabling kinds of verification that would otherwise not be possible, such as in-circuit emulation, or runs that go deep into the state space of the design that would take hours or even days to reach in simulation.
Using FPGAs can also make stimulus creation a lot simpler by enabling the use of real world stimulus coming from peripheral interfaces, audio or video streams etc. But this is a path not for the faint of heart or those who are unprepared.
There are three primary ways in which people usually accomplish this. This first is to buy an emulator or simulation accelerator from one of the EDA vendors (I will discuss the differences between these approaches in a future blog).
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