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Faster IC Designs Without Using a Clock and With Delay Insensitive ResultsEDA Thoughts - Daniel PayneDec. 10, 2010 |
Digital designers are taught on day one that they must use synchronous logic design which employ a clock to synchronize all events in their IC design, and so it has been for decades.
Unless of course you have ever designed a DRAM or SRAM memory where self-timed logic is used to squeeze out the ultimate in performance. I started out designing DRAM circuits at Intel (when they were still in the DRAM business) and was delighted to learn that my chip was using self-timed logic to increase performance and simplify the interface requirements when the memory was placed on a board.
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