Industry Expert Blogs

In a Jan. 10 announcement of new Silicon Realization verification capabilities, Cadence has promised to "extend metric-driven verification from digital simulation to formal model checking." Here's some more detailed information about what that means and how it can help design and verification engineers meet their verification goals.

Many IC design teams use metric-driven verification (MDV) for simulation. The concept is simple; you capture your verification intent in an executable verification plan (vPlan), and as verification progresses you track coverage metrics, most notably code coverage and functional coverage. The plan can also track assertions, checks, and time-based data points. This makes it possible to determine when high-quality verification closure has been achieved, answering the toughest of all verification questions, "am I done yet?"

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