Two main languages, both IEEE standards, are in use today for constrained-random verification - SystemVerilog and the e language. Which is best, under what circumstances? Geoffrey Faurie, a member of the Functional Verification Group at STMicroelectronics, has some definite opinions about that question.
Faurie's team is responsible for evaluating and recommending new verification methodologies. He's a long-time user of e and Specman, and has more recently used SystemVerilog with the Open Verification Methodology (OVM) and its successor, the Universal Verification Methodology (UVM). Today at STMicroelectronics, he noted, about 85 percent of IP verification engineers use e and the remaining 15 percent use SystemVerilog for constrained-random verification.
Faurie says he's noticed an approximate productivity drop of 30% when teams switch from e to SystemVerilog. On the other hand, he acknowledges the value of UVM in providing a standard for verification IP. "We have different advice" for the STMicroelectronics verification teams, he said. "If there is a strong interoperability requirement for design or verification IP to work natively on all EDA vendor simulators, we advise to go with SystemVerilog. If not, we advise engineers to stay with e."
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