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User View: How Metric-Driven Verification Improves ASIC and FPGA QualityIndustry Insights Blog - Richard Goering , CadenceJan. 24, 2011 |
To keep bad chips and boards from going into the field, automatic test equipment (ATE) has to be reliable. That's why Teradyne, a major ATE provider, takes verification quality very seriously. With help from Cadence, Teradyne converted from a "home grown" methodology and made the switch to metric-driven verification (MDV) several years ago.
In a Jan. 10 press release announcing a Cadence Silicon Realization verification capability, a Teradyne representative noted that MDV has helped his company improve predictability and quality for both ASICs and FPGAs. I talked to Vlad Kheyfets (right), semiconductor design engineer at Teradyne, to get some more details about that company's experience with MDV.
