Transaction-based acceleration can speed up simulation hundreds of times, but you need to develop a good strategy to take full advantage of it, according to a paper authored by Cadence and Broadcom and presented at the recent DVCon conference. The paper detailed Broadcom's experience using transaction-based acceleration with the Cadence Palladium hardware verification platform.
The paper was titled "Transaction-Based Acceleration - Strong Ammunition in Any Verification Arsenal." It was presented by Chandrasekhar Poorna, principal engineer at Broadcom. This and other archived papers will be available at the DVCon web site April 18.
Some quick background: With simulation acceleration, the design under test (DUT) is synthesized into hardware while a simulation testbench runs on a workstation. While basic acceleration traditionally involves a signal-level interface between the software running the testbench and the hardware acceleration platform, transaction-based acceleration brings this interface up to the transaction level, greatly reducing communication overhead and improving performance even further.
As a verification methodology, it provides a bridge between simulation and in-circuit emulation. I provided some further background information on transaction-based acceleration in a previous blog post.
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