Industry Expert Blogs

System-on-chip (SoC) design teams have learned they can be much more productive by acquiring processor and interface IP. But most teams still build their own memory and storage controllers - a task that is becoming more difficult, and returning fewer benefits, as complexity grows. Memory and storage management is a new frontier for IP, and it's front and center in the emerging Cadence SoC Realization strategy.

Cadence this week (April 11) is announcing the first DDR4 IP solution, including controller IP, soft and hard PHY IP, memory models, verification IP, and tools and methodologies. Along with that announcement, Cadence is further detailing its SoC Realization strategy.  A key tenet of the EDA360 vision outlined last year, SoC Realization is about the creation of individual SoCs, and IP integration is a central part of it.

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