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The problem: To move a single lane variable data rate SerDes (serializer-deserializer) from a 65nm process to a 45nm process, achieving a maximum performance of up to 10.3 Gbps. This is a large piece of complex mixed-signal IP with handcrafted analog circuits. Circuit performance and robustness are critical and must be maintained in the migrated implementation.

The original design consisted of over 30 blocks with a hierarchical device count of around 30,000 (about 200,000 flat).

After the first migration, business opportunities arose requiring the same SerDes IP to be moved to two further different 40nm processes.

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