Cache coherency is essential for any processor-based system that uses cache memory. And now, it is moving from software into hardware in multi-processor mobile devices, due to ARM's new AMBA 4 Coherency Extensions (ACE). What does that mean from a verification standpoint? Newly available verification IP (VIP) specifically for the ACE protocol provides an answer.
Primarily aimed at multi-processor ARM Cortex-A15 designs for mobile devices, ACE provides hardware-level cache coherency. Cadence today (June 6, 2011) announced its support for ACE with an AMBA 4 ACE verification solution.
The shift from software to hardware cache coherency is "pretty dramatic and significant," according to Pete Heller, senior product marketing manager for Verification IP and Interconnect at Cadence. Why is it happening? "Software cache concurrency schemes take too many cycles and consume too much power," Pete said. "To gain back those cycles and to reduce power consumption, you need to move that into hardware." This is particularly true in mobile computing applications, where "you need to devote your cycles to making the apps responsive while at the same time avoiding major drains on battery life."
Click here to read more ...