Wireless, networking, storage, computing and FPGA applications have been moving aggressively to advanced process nodes to take advantage of lower power consumption, improved performance and area reduction. Today, most of these applications integrate a significant amount of analog/mixed signal (AMS) or RF together with digital circuits. Since AMS often occupies over 50% of the chip area, applying traditional, conservative approaches when migrating to an advanced node diminishes and possibly eliminates these benefits.
Due to significant changes in physical effects and device performance, a simple migration to next node is not practical. AMS circuits need to be optimized and often completely redesigned to meet performance specs. This requires design companies to have an AMS IP flow fully ready at the same time as, or even earlier than, the digital flow in order to realize silicon at advanced process nodes.
A survey of 561 predominantly analog and mixed-signal designers and CAD engineers from over 150 companies, collected during Cadence worldwide Mixed-Signal Seminars in March 2011, confirmed that 65nm has became mainstream for mixed-signal. The survey also showed strong AMS design activity at 40 and 28nm.
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