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Industry Expert Blogs
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What Does SystemC Mean for Design and Verification?Functional Verification Blog - Tom AndersonAug. 23, 2011 |
My colleague Jack Erickson recently published in the Cadence System Design and Verification Community a blog post entitled "IP Cannot Be an Efficient Abstraction Level without SystemC!" When I saw the title, my immediate reaction was to write a complementary post called "SystemC Cannot Be an Efficient Abstraction Level without IP!" This caused me to think some about the industry momentum toward using SystemC rather than traditional RTL as a design language. I chose a more general title because there are three key points I want to hit.
