In their presentation at the recent SystemC Japan conference, Renesas Micro Systems, Inc. (RMS) stated 2 SystemC "beginners" completed a 17M gate design in 8 months, achieving first-pass timing closure at 650 MHz targeting 40nm.
Two thoughts came to my mind:
- Wow!
- What is their ROI of migrating from an RTL-driven methodology to a SystemC-driven methodology?