Industry Expert Blogs

As process technology pushes forward from 40 to 28 nm, unavoidable scaling effects are changing the electrical characteristics of the basic elements—the transistors and interconnect wires—with which chip designers must work. These new transistor-level challenges, in turn, are bringing about changes in the architecture, implementation, and performance of system-level ICs. And those chip-level changes are creating a new landscape in which system designers must find their way.

Since the early days of the IC, process scaling has promised unbroken progress. In each new generation the minimum feature size would decrease by about a third, and hence the area occupied by the smallest transistor would shrink by a factor of two. At the same time maximum clock frequency for a given digital circuit would increase, and power consumption would drop, both by relatively stable and significant factors. In each new generation, then, chip designers could offer system developers new ICs that integrated more functions, ran faster, and still burned less power. But those days are gone.

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