The photo at right shows a test socket and chip destroyed by thermal runaway. Can this really happen? Yes, it can and it sometimes does, if test power is significantly greater than functional power.
To get a handle on this problem I talked to Bassilios Petrakis, product marketing director for Design for Test (DFT) at Cadence. "Most people think about power in terms of its actual applications," he told me. "But people don't spend a lot of time thinking about what happens when you test a chip." In verification, he noted, engineers will generally test a chip in its normal functional modes. "Equally important, but not as well looked at, is what happens when you put a chip on a tester."
What can happen - if you use automatic test pattern generation (ATPG) vectors that aren't power-aware -- is that test power can end up being several times higher than the functional power the chip was designed for. The problem is too much switching. When you load the scan chains, flip-flops trigger. When you capture the responses, they trigger again. Too much switching activity can overstress the chip, potentially damaging it or, worst case, blowing it up.
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