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180nm FTP Non Volatile Memory for Standard CMOS Logic Process
Industry Expert Blogs
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System-Level Low Power Design - What Will it Take to Move There?Industry Insights Blog - Richard Goering , CadenceApr. 19, 2012 |
While many low-power design techniques are available to IC designers, the greatest potential for power savings is at the system level, where both software and hardware can be considered. So what's standing in the way of system-level low power design, and what needs to happen to make it practical? Qi Wang, group director for solutions marketing at Cadence, provided some answers in a recent talk at the Electronic Design Processes Symposium (EDPS 2012) in Monterey, California.
The presentation was titled "Low Power Design: Is the Problem Solved?" Wang started his talk by noting that power requirements have different drivers in different vertical markets. In the mobile area, the concerns are battery life and cost; in data centers, the concerns are power efficiency and cost of ownership.
