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TSMC-Cadence Collaboration Helps Clarify 3D-IC EcosystemIndustry Insights Blog - Richard Goering , CadenceJun. 05, 2012 |
Perhaps the most challenging question about 3D-IC design is what gets done when, by which kind of provider. With its recently introduced chip-on-wafer-on-substrate (CoWoS) process, TSMC has taken a step towards clarifying what the 3D-IC ecosystem might look like. And Cadence helped refine the methodology and provided design tool support, as announced today (June 4, 2012) at the Design Automation Conference (DAC), where Cadence and TSMC are offering a joint tutorial on 3D-ICs.
CoWoS came to light in March with the announcement of an Altera test vehicle developed using this process. TSMC defined CoWoS as "an integrated process technology that attaches device silicon chips to a wafer through a chip on wafer (CoW) bonding process. The CoW chip is attached to the substrate (CoW-On-Substrate) to form the final component. By attaching the device silicon to the original thick wafer silicon before it finishes the fabrication process, manufacturing-induced warping is avoided."
