xWhat will it take to achieve silicon success at 28nm and below? That was the question put to a panel of experts at a Cadence-sponsored breakfast at the Design Automation Conference (DAC 2012) June 6, where speakers from IBM, Cadence, ARM, Samsung, and GLOBALFOUNDRIES shed new light on business and technology challenges and solutions.
The panel was titled "The Path to Yielding at 2(x)nm and Beyond," and was moderated by Steve Leibson (leftmost in photo below), marketing director at Cadence and author of the EDA360 Insider blog. It would be hard to find a more qualified panel. Panelists were as follows, listed as shown from left to right:
- Gary Patton, vice president of IBM Semiconductor Research and Development Center
- Chi-Ping Hsu, senior vice president of R&D, Silicon Realization Group, Cadence
- Dipesh Patel, deputy general manager, ARM Physical IP Division
- KM Choi, senior vice president of the Semiconductor Business at Samsung Electronics
- Mojy Chian, senior vice president, Design Enablement, GLOBALFOUNDRIES
"Success at 2(x)nm nodes is a difficult topic, but here are some of the most experienced people on the planet who can advise you where the potholes are going to be, because they've already stumbled into a few of those potholes themselves," Leibson said.
Click here to read more ...