English
CPU Designed for the Next Generation of High Performance Wireless Communications and Networking
Industry Expert Blogs
|
MIPI LLI Webinar on EE Times, Wednesday, 27 JuneArteris Connected Blog - Kurt ShulerJun. 25, 2012 |
Hezi Saar (Synopsys' M-PHY PM), Philippe Martin (Arteris Senior Fellow and LLI God) and I will be hosting an EE Times webinar on the MIPI Low Latency Interface (MIPI LLI) and M-PHY on Wednesday, 27 June, at 9 am Pacific time.
Related Blogs
- Reuse ROI Proof Point, USB 3.0 SSIC across MIPI M-PHY with a slice of HAM
- Come run with the big dogs at PCI-SIG Devcon 2016!
- Cadence First to Demo Complete M-PCIe PHY and Controller Solution at MIPI and PCI-SIG Conferences
- MIPI Alliance Meeting Reflects the Rapid Growth of the Mobile Market
- Low Power, Phones, Tablets and PCIe, Oh My!