Last week some of my team participated at the PCI Express Developer’s Conference in Santa Clara, California. There were demonstrations at our booth and a well attended presentation given by our engineering expert on “Designing to the New PCI Express 3.0 Equalization Requirements”. This conference is essential for anyone working on PCI Express, to learn about new features (L1 substates) and use models (SSD, storage), updates on the specifications (PCI Express 4.0) and to network with industry experts. Below is a summary of the conference.
Proposals for an evolutionary path to PCI Express 4.0 @ 16Gbps were presented. Here the goal is to enable infrastructure re-use while addressing major challenges in scaling data rate with channel improvements and better connectors.