Power consumption and area are commonly considered in choosing an embedded SoC processor, but another major factor is often overlooked in such an evaluation: the code density of the processor’s instruction set architecture (ISA).
Code Density’s Effect On Power Consumption
A denser instruction set yields smaller code, which in turn requires fewer instruction fetches. This has a major impact on efficiency, because the energy used to fetch an instruction from on-chip memory is much greater than that required for the CPU to execute that instruction.
How much greater? The 2010 Stanford dissertation study by James Balfour on Efficient Embedded Computing showed that for a typical 32-bit RISC processor, an instruction fetch from a 2 Kbyte on-chip cache consumes 6.8 times more energy than a 32-bit add operation (in a typical 45nm CMOS process).
Another study by Dally et al published in IEEE Computer found that 42% of a typical embedded processor’s energy consumption comes from instruction fetching, and only 6% is consumed by performing the actual arithmetic operations.
Both these studies used a small, on-chip cache. When instructions more realistically need to be accessed from larger, on-chip or even worse off-chip memory, the impact is magnified, and the factor of 6.8x can go to 50x or more.
The conclusion here is clear: using an ISA that requires fewer instructions is a much bigger energy saver than simply selecting a processor that executes more efficiently.
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