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This is the third part of a three part series discussing SystemVerilog interfaces and strategies for dealing with parameterization.

In the first part of this series the basic concepts of SystemVerilog interfaces were introduced and the problems that parameterization of those interfaces introduce to testbench code was described.  In the second part the method of using an accessor class to shield the VIP code from the parameterization effects was described, but this solution imposes new restrictions on VIP access to that interface.  In this final post of this series a process is introduced that allows the testbench to make use of parameterized interfaces without imposing any limits on the way that the VIP can access the interface that it is provided.

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