Industry Expert Blogs

Recently I worked with a user who was responsible for verifying an AXI interface. This user was coming from a non-UVM background, but was conversant with SystemVerilog. The user was faced with the challenge of learning UVM and coming up to speed with an understanding of the VIP, both at the same time, under tight verification timelines. Figuring out how much UVM knowledge would suffice to integrate the VIP, then coding the testbench around the VIP to run and debug the verification environment, appeared to be the first few challenges. I proposed a simple approach: let us begin with a simple directed testbench, get some AXI tests going using the VIP, gain some confidence in terms of understanding the core functionality of the DUT and VIP and, in parallel, learn some UVM basics as well. Later, I suggested, he can move on to advanced testing using constrained-random verification where he will need more advanced UVM knowledge, for instance, the application of virtual sequences.

Here are the steps used to integrate Discovery AXI VIP to start verification of an AXI interface in a simple directed environment. This is correct approach for directed testing that achieves best performance as well.

Click here to read more ...