Many engineers today use C language software running on an embedded processor model to build testbenches for hardware verification. This "software-driven verification" technique is an ad-hoc methodology that often uses home-grown tools. But it's something you may hear more about in 2013, as software becomes a more and more important part of the overall SoC development process.
In a column posted just before Christmas 2012 at Electronic Design magazine, Frank Schirrmeister (right), product marketing director for the System Development Suite at Cadence, wrote that "it is time for software-driven verification to be adopted at a faster rate in 2013." He noted that many customer projects use processors to execute test software in conjunction with the hardware block that's being verified. In some cases, teams use a dedicated separate processor for those tests, which functions much like a built-in self test (BIST) capability in silicon.
Intrigued, I talked with Schirrmeister about software-driven verification and its advantages and challenges. He noted that there are three aspects to software-driven verification. One is getting hardware and software to work together. Another is using software to develop testbenches for hardware. A third is using software to model the environment in which the chip resides.
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