While formalized methodologies now exist for many aspects of functional verification, verification planning is still largely an ad-hoc process. Yet verification planning is becoming increasingly important as chips get more complex. At the recent DVCon 2013 conference, a panel of verification experts discussed why verification planning is important, what the challenges are, and what "best practices" can be applied to verification planning.
The panel, titled Best Practices in Verification Planning, was part of a Cadence-sponsored luncheon Feb. 27. The panel was moderated by John Brennan, product director for verification at Cadence. Panelists were as follows, shown left to right (after Brennan at the podium) in the photo below:
- Jason Sprott - Chief Technology Officer, Verilab
- Mike Stellfox - Verification Fellow, Cadence Design Systems (see video clip at the end of this post for brief post-panel interview)
- Ambar Sarkar - Chief Verification Technologist, Paradigm Works
- Neyaz Khan - Distinguished Member of Technical Staff, Maxim Integrated
- Vigyan Singhal - President and CEO of OSKI Technology
- Meirav Nitzan - Lead Verification Methodologist, Xilinx
Verification planning is still an "art form," Brennan noted at the beginning of the panel. "To get a good verification plan together takes a significant amount of work," he noted. "There are so many human factors that it is really hard to codify it and make it a true science."
Here's what panelists had to say about the three main points that came up in the panel - why planning is needed, what the challenges are, and what the best practices are.
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