A presentation at the DesignCon 2013 conference illustrated a new methodology that speeds timing closure for ASIC and SoC designs with hundreds of millions of gates. Called "multi-level physical hierarchy design," it overcomes many limitations of conventional "two level" hierarchical flows. The GigaScale option in the Cadence Encounter Digital Implementation System supports this new methodology.
Here's some quick background. Synthesis and layout optimization for timing closure are flat in nature, meaning that the entire design is treated as one physical entity. These optimization methods consume more and more memory, and require longer run times, as chip designs get bigger. As a result, high-performance multi-million gate designs today are commonly optimized by partition-based hierarchical methods. These approaches divide a large chip into sub-chips or partitions that are small enough to be optimized as a flat design.
With a conventional two-level physical hierarchy flow, each partition can be further divided into more partitions. However, hierarchical design flow steps - such as feedthrough (for managing channel congestion), pin assignment, and timing closure - are accomplished one level at a time, potentially leading to sub-optimal results. For example, pin assignments made from observing just one level of hierarchy could lead to infeasible floorplans.
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