The TSMC 2013 Technology Symposium, held April 9 in San Jose, California, brought good news for anyone interested in advanced node or 3D-IC technologies. Keynote speakers noted excellent yields and significant progress in 20nm planar, 16nm FinFET, and Chip-on-Wafer-on-Substrate (CoWoS) technologies, as well as promising development work with 10nm FinFET and true 3D-IC stacking.
Keynote speakers included Morris Chang, TSMC founder and CEO, who provided a semiconductor industry overview and company update (see blog post here). Subsequent keynote speeches were given by TSMC executives Jack Sun, Vice President of R&D and Chief Technology Officer; Cliff Hou, Vice President of R&D; and J.K. Wang, Vice President of Operations, 300mm Fabs.
Sun began his talk with a look at the human brain, a 3D structure that has the equivalent of about a trillion transistors and only consumes 20 watts. State-of-the-art systems on chip are nowhere near that performance and power efficiency, so how can we get closer? "Going into the future we don't have to resort to monolithic integration alone," he said. Instead, we can combine chip scaling with copper through-silicon via (TSV) technology and close the interconnect gap between chips.
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