Presentations at the Electronic Design Process Symposium (EDPS) April 18, 2013 gave a realistic look at the promises and limitations of electronic system level (ESL) design. Speakers noted that ESL tools are used for the lower levels of the software stack, but typically not for applications development. There is no magic tool that will fully automate hardware/software partitioning. Even so, ESL technology can be of tremendous value if properly used.
Now in its 20th year, EDPS is a small but influential IEEE workshop that brings together movers and shakers in the electronic design methodology community. Cadence was a gold sponsor this year. ESL presenters and panelists were as follows, as shown left to right in the photo below. Gary Smith, chief analyst at Gary Smith EDA, moderated the panel that followed the presentations.
- Guy Bois, founder and president, Space Codesign
- Frank Schirrmeister, group director of product marketing for the System and Software Group at Cadence
- Michael McNamara, CEO, Adapt-IP
- Gene Matter, senior applications engineer, Docea Power
- Gregory Wright, member of technical staff, Alcatel-Lucent
EDPS keynote speaker Ivo Bolsens, CTO of Xilinx, was not officially part of the ESL session - but his keynote was a great lead-in to it. Bolsens talked about the "all programmable SoC" and pointed to the Xilinx Zynq-7000 Extensible Processing Platform, noting that it has programmable logic, I/Os, DSPs, and CPUs. This platform, he said, provides "different levels of programmability so you can tailor the platform to the embedded apps you are targeting." He also talked about the Xilinx Vivado high-level synthesis tool and its role in hardware/software development.
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