It's not too early to start thinking about the 10nm process node and beyond - but such advanced process nodes will require a significant change in the semiconductor design ecosystem, according to Jongwook Kye, fellow for lithography modeling and architecture at GLOBALFOUNDRIES. At the recent CDNLive Silicon Valley 2013 conference, Kye made the case for a new level of collaboration called Design Technology Co-Optimization (DTCO).
Kye's presentation was titled Technology and Design Co-Optimization for 10nm and Beyond. The presentation had 9 co-authors, including Jason Sweis of Cadence. Presentation slides are available at the CDNLive Silicon Valley proceedings site (after logging in, look for session AVD201 under Advanced Node/3D-IC).
Kye began his presentation by noting that process technology development and design are separate "islands," and that technology developers "ship" information to designers using process design kits (PDKs). But this one-way delivery is no longer good enough. "We have to work together with design-aware technology and technology-aware design," Kye said. "What I propose is not a delivery [of PDKs], it is DTCO."
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