Bringing 64-bit ARMv8 performance into the enterprise and server market, ARM announced the AMBA® 5 CHI (Coherent Hub Interface) specification at the Design Automation Conference (DAC 2013) June 3. To help ease adoption, Cadence is offering verification IP (VIP) that simplifies functional verification, provides interconnect performance analysis, and creates verification test suites for multi-core interconnects.
The AMBA protocol is an open standard, on-chip interconnect specification for the connection and management of functional blocks in a system-on-chip. You may already be familiar with AMBA 4 and the protocols it supports - ACETM (AXI Coherency Extensions), ACE-LiteTM, AXI4TM, AXI4-LiteTM, and AXI4-StreamTM. The earlier AMBA specifications defined popular interface protocols including AXITM, AHBTM, APBTM, and ATBTM.
Now there's a new protocol - AMBA 5 CHI. It is used by the ARMv8 Cortex®-A57 and Cortex-A53 processors, the CoreLinkTM CCN-504 Cache Coherent Network, and the CoreLink DMC-520 Dynamic Memory Controller. The AMBA 5 CHI interface architecture enables higher performance coherent hubs with many processors and the high data rates common in enterprise markets. It supports high frequency, non-blocking coherent data transfer between many coherent processors. The interface also supports distributed level 3 (L3) caches, high data rates of I/O coherent communication, and Quality of Service (QoS).
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