One of the hottest (or should I say coolest – because low power is so important) new standards is PCI Express® (PCIe) over M-PHY, or M-PCIe. To implement it properly, it’s essential that the controller and PHY work well together as the interface specification between them is, to put it mildly, loosely defined.
We just finished the PCI-SIG 2013 conference at the Santa Clara Convention Center, and our M-PCIe demo was a big hit. We actually demoed it for the first time the week of June 17, 2013, at the MIPI Alliance’s European Meeting in Warsaw.
It was fitting that Cadence would be the first to demonstrate the PHY and controller IP with high-speed links across M-PHYs. Cadence was one of the initial sponsors of this ECN. The Cadence design team actively participated in the discussions and contributed to the specification. Our design is a native RMMI based implementation, unlike implementations that convert PCIe to M-PCIe using a shim layer. The shortcut via the shim might be tempting, but does not help realize the power advantages of the protocol!
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