Cadence Verification IP (VIP) provides solutions for verifying compliance and compatibility of protocols. All VIPs include highly configurable and flexible simulation models of all protocol layers, devices and transaction types. Cadence VIPs also support integration and traffic generation in all popular verification environments.
During the past year, I have seen engineers struggling with debug for VIP based simulations. The questions that bother them most are:
How can I generate tests quickly and efficiently to ensure that the design is compatible with standard Interface requirements?
How are extensive protocol checks and coverage built into Cadence VIP, ensuring the high quality of VIP design under test?
How can I make the best use of trace files in debugging VIP design simulations?
How can I create, configure and instantiate VIPs in the testbench?
In this blog, I will talk about how Cadence staff and engineers are developing some app notes to help users debug using trace files. I will give you references to complete documents for following VIP - AHB, USB2.0, PCIE2.0, USB3.0, SSIC and LFPS Signaling in USB3.0.