In my last post, I discussed highlights from the recent 2013 PCI-SIG Developer’s Conference including PCIe 4.0, OCuLink and M-PCIe. I also provided information on the world’s first M-PCIe interoperability demo, which showcased M-PCIe solutions from Intel and Synopsys working together. I concluded with the promise of information on the second M-PCIe demo from Synopsys and more information on M-PCIe.
If you’re new to M-PCIe, let’s start with some highlights:
- What is M-PCIe (sometimes aka Mobile Express)?
- M-PCIe takes the well-understood PCI Technology, used in the industry for 3 decades, and marries it with a proven mobile technology to reduce power
- M-PCIe is an ECN to the PCI Express specification that combines the robust PCI Express protocol with the low-power MIPI M-PHY
- M-PCIe is a PCI-SIG, not a MIPI, protocol
- What benefits will M-PCIe give the consumer?
- Helps usher in a new generation of high performance, lower power devices enabling mobile devices to run all day on a single battery charge without sacrificing performance or features
- Delivers proven technology quickly to the fast-moving mobile device market. M-PCIe leverages current investments in PCI Express IP, software and know-how while reducing the time-to-market and lowering the implementation risk
- Enables new system architectures to reduce power
- What is Synopsys doing for M-PCIe?
- Synopsys launched our Mobile PCI Express solution at PCI-SIG DevCon 2013, which includes M-PCIe controllers and MIPI GEAR 3 M-PHYs
- Synopsys is committed to bringing proven technology to the market quickly and we’ve worked together with Intel to showcase the technology and do interoperability demos (see previous post)
For our second M-PCIe demo, we wanted to showcase the performance of our M-PCIe controllers and MIPI GEAR 3 M-PHYs while also showing that M-PCIe is using the standard PCI Express protocol. We decided to use our PCIe Gen3 eDMA demo and updated it to use an M-PCIe endpoint. Since there are no systems out there that have an M-PCIe Root Complex, we implemented an M-PCIe connection via a switch between the standard PC’s PCIe slot and the M-PCIe Endpoint device. The diagram below is the block diagram for the hardware in our demo overlaid onto the Synopsys HAPS FPGA prototyping system.
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