Industry Expert Blogs

Recently Bill Dally, nVidia’s Chief Scientist & SVP of Research, and a professor of electrical engineering and computer science at Stanford University, has been out speaking quite a bit including a “short keynote” at the Design Automation Conference and a keynote at ISC 2013. The DAC audience is primarily EDA tool users and EDA tool developers. ISC’s attendees are high performance computing (HPC) experts. While the DAC talk focused on designer productivity, the ISC talk honed in on the challenges of exascale system design. The topics, in fact, are highly interrelated.

As Dally pointed out in his presentation at DAC, the key to greater design productivity is to work at higher levels of abstraction. While this should seem obvious, it does run a bit counter to the behavior of many engineers. Most designers work hard to squeeze out every bit of power, performance, or area (PPA), depending on the importance of each design constraint for their end product. This often means starting with a proven piece of IP in an RTL form and then changing it to “perfect it” for their needs. That perfection takes time, not just on the editing, but on the subsequent implementation and verification efforts. It would be much faster if the designer used all the hardened IP they could find. While the design will not be quite as good on overall PPA it would be ready for tape-out many months sooner.

Click here to read more ...