Memory models are essential for SoC verification, and this week (August 6, 2013) at MemCon, Cadence is announcing the industry's first memory models for five emerging standards. This blog post provides some background about two of those standards -- Wide I/O 2 and Hybrid Memory Cube (HMC) -- both of which are aimed at 3D-IC architectures. The other supported standards are LPDDR4, eMMC 5.0, and LRDIMM.
These five new memory interface standards are important because memory has become a major bottleneck with respect to performance and power goals. Specialized memory interfaces such as Wide I/O, LPDDR4, and HMC have emerged to recapture the power and performance that tomorrow's devices will demand. But you can't take advantage of these benefits without reliable memory model verification IP (VIP) that allows you to verify that your SoC works correctly with the memory that you're using.
In general, Wide I/O 2 targets mobile devices while HMC aims at high-performance computing. Why support these emerging standards? "The whole memory market is moving to a 3D approach," said Scott Jacobson, senior product marketing manager at Cadence. "Whether you're in the high-performance space or a mobile space, we are supporting and helping to push these standards along."
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