In Part 1 of this panel discussion on verification, the experts talked about the state of verification and the progress that has been made.
In Part 2 the subject broadened to the increasing areas in which verification has to be performed, including power and software. In this third part the discussion turns to the how far formal methods can go in addressing the challenges facing SoC design.
Taking part in this discussion are: Paul Martin, senior manager of debug, trace, and performance modeling at ARM; Rajeev Ranjan, CTO, and Oz Levia, vice president of marketing and business development at Jasper Design Automation; Harry Foster, chief verification scientist at Mentor Graphics; and Viresh Paruthi, senior technical staff member at IBM.
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