Increased interest in on-chip network IP is without a doubt directly correlated to the increase in SoC complexity and performance over the past few years. Some SoC design managers even have gone so far as to say that the success of their SoC program is directly related to their ability to implement an on-chip communications network. Underestimating the importance of the on-chip network has caused many SoC programs to miss their performance targets, schedules, or even be canceled altogether.
Why? The on-chip network touches most aspects of the design, from early SoC architecture exploration all the way through to back-end layout. This includes interface protocol support (e.g. AMBA, OCP, PIF, etc.), performance, memory scheduling, quality-of-service, power management, security, system domain partitioning, verification and more. Get any one of these wrong in the SoC design and you will have a chip that either underperforms or, even worse, one that does not work at all.
What’s so special about a NoC and how does it help SoC design teams deal with all this complexity? Unfortunately, before answering the question, I need to discuss terminology. Discussing terminology in this case is not simply an academic exercise, but essential for getting to the root of the question. A NoC typically refers to a specific network topology implementation using links and routers to form connections between IP cores. A NoC is also characterized by packetizing and serializing the data (i.e. the networking analogy). When using the term NoC, there is potential for confusion because some understand it to only mean the process of packetizing/serializing the data, while others mean the entire on-chip communications network. The implementation of a NoC also varies with some using simple muxes/demuxes with retiming for the topology structure, while others implement actual routers.
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