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Bring together three of the best known and most opinionated voices in EDA - along with a Cadence R&D executive - and what do you have? A spirited panel discussion on electronic system level (ESL) functional verification, along with a call for a "top down" verification approach guided by requirements and use cases.

The panel took place at the System-to-Silicon Summit held Sept. 26, 2013 at Cadence headquarters in San Jose, California. Brian Fuller, editor-in-chief at Cadence, served as moderator. Panelists were as follows, shown left to right in the photo below:

• Ziv Binyamini, Corporate Vice President , R&D, System Solutions at Cadence
• Brian Bailey, consultant and blogger
• Jim Hogan, veteran EDA investor
• Gary Smith, Chief Analyst, Gary Smith EDA

The panel discussion began with a presentation in which Gary Smith stated that a "true" ESL design and verification flow now exists. (This is essentially the same message that was conveyed in an August 2013 webinar, reported in my recent blog post). Basically, the flow started to emerge in 2011, but in 2012 it became evident that power information was lacking. The lesson of 2013 was the need for emulation and acceleration in the flow. The ESL flow is now working but is put together with "glue and bailing wire," Smith said.

Smith also commented on what he called the "crisis situation" in the embedded software tools market, in which most of the major players have gone out of business or been acquired. "Embedded [software] will be part of the EDA business just as IP is now part of the EDA business," he predicted.

Below are some excerpts from the panel discussion that followed.

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