The Plug-and-Play IP initiative is Xilinx’s response to the growing use of multiple IP cores from diverse internal and 3rd-party sources to design systems with All Programmable devices. Plug-and-Play IP cores provide a simple yet powerful way to improve designer productivity by supporting easier IP reuse. To ensure portability and interoperability among IP offerings from Xilinx and its Alliance members, Xilinx has taken a standards-based approach to delivering proven, easy-to-use IP cores. The three critical standards that enable the development of Plug-and-Play IP are:
- The AMBA AXI4 interconnect protocol developed in conjunction with ARM
- The IEEE P1735 encryption and rights-management standard for design IP
- The IP-XACT XML Schema specifying IP metadata and interconnection from Accellera and based on IEEE 1685-2009
The Xilinx Plug-and-Play IP initiative leverages these industry standards to accelerate IP integration in system-level designs.
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