A recent post on Cadence's Interconnect Workbench (ICW) caught my attention. ICW is a tool targeted toward the growing and evolving SoC verification market. Interconnect buses like AXI, AHB, and Wishbone form the backbone of SoC hardware. The throughput and latency of these buses in resolving requests from IPs has a major impact on SoC hardware/software performance.
Having confidence in one's interconnect hierarchy and arbitration mechanism early in the flow is crucial to an SoC's success. The ICW tool has two flavors. One is an aid for performance verification, while the other is focused on functional verification. I was more inclined to dig deeper into the performance verification aspect. Essentially, the tool accepts traffic profiles for tuning traffic generators to pump traffic (data) into the interconnect from any of the masters plugged into the fabric. It is quite possible to develop behavioral models on top of the traffic generators, or verification IP modules to mimic TCP/IP streams or the block transfer of a file over the USB protocol, since these have predictable memory access patterns. By comparison, modeling CPU-based traffic is definitely a challenge, because this depends on the access pattern of the algorithm being executed.
I believe a tool like ICW can help users overlap and synchronize traffic streams to increase concurrency in the system and span the worst- to best-case scenarios. This also makes it easier to study or verify arbitration systems and to play with the priority settings of the various IP blocks.
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