When you're in a rapidly expanding marketplace that is coming into mainstream adoption, you want to have the most complete solution possible. And that is some of the thinking behind the Cadence acquisition of high-level synthesis (HLS) pioneer Forte Design Systems, which was announced Feb. 5 and is now completed.
Unlike RTL synthesis or "logic synthesis," HLS works at a much higher level of abstraction. Both the Cadence C-to-Silicon Compiler and the Forte Cynthesizer products take in IEEE 1666 SystemC code and constraints and output RTL code. Compared to conventional RTL design, the HLS methodology offers much faster time to market, faster and easier verification (fewer lines of code means fewer bugs), and an ability to quickly generate different micro-architectures and compare power, performance, and area.
A decade ago, HLS was pretty much limited to a handful of large Japanese consumer product companies. But now, said Michał Siwiński, vice president of product marketing at Cadence, it has spread across the globe and it enjoys strong adoption in many systems and semiconductor companies for a wide variety of applications. The chart below shows some of the end applications served by C-to-Silicon Compiler, which can handle datapath, control, and mixed datapath and control logic.
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