Clock/Data recovery (CDR) is a tricky logic to implement correctly. To verify the clock/data recovery logic implemented in designs, the corresponding verification infrastructure needs to be modeled correctly.
This presentation aims to present the various issues faced for modeling CDR behaviorally along with their solutions.
The presentation starts off by explaining the need for CDR in the context of serial interfaces. It then explains how CDR would be done in an ideal scenario. Real issues like Jitter and PPM/Drift are then introduced along with techniques for handling these effects. Finally, a flow chart explains how an accurate behavioral model can be constructed.