This blog is useful for all those who are familiar with verification development – but want to get better at it. It is useful for design engineers as it will help them evaluate (and push) their verification teams to deliver a better solution. It is useful for verification engineers also, as it will help them better their skills.
Why is it important to have a great process for development of Verification IP?
Verification plays a major role in any chip design project. Within that, functional verification takes lion’s share of any design cycle, 70% by some estimates. Functional verification completeness is extremely critical. Following the wrong process for developing verification IP can cause you to miss verifying some features. This can cause chip failure and cost the company millions of dollars. It has been noted that close to 70% of chip re-spins are typically due to functional bugs although that percentage has come down to ~50% in recent times. Thus following a good process with lots of planning is essential for development of world class verification IP.