Single Port, Ultra Low Leakage, GF 22FDX, Register File Compiler
Industry Expert Blogs
![]() |
The Risks & Rewards of Early TapeoutEETimes Blog - Mike Bartley, Founder & CEO, TVSJul. 23, 2014 |
Verification remains a key issue in system-on-chip development. The time taken to verify a high-density SoC design to a high level of confidence can lead teams to think the unthinkable. One of these counterintuitive options is to not exhaustively verify a chip before taping out but use the resulting silicon itself as a cornerstone of the verification process.
A panel session at the recent 51st Design Automation Conference was more or less evenly split on the approach. Early tapeout has its attractions but carries risks and potential costs that go way beyond the price of a mask set for a device that is highly unlikely to make it to production.
Related Blogs
- Digitizing Data Using Optical Character Recognition (OCR)
- Moortec "Let's Talk PVT Monitoring" Series with CTO Oliver King
- ARM vs RISC-V: Beginning of a new era
- Let's Talk PVT Monitoring: Process Detection & Variability
- Secure-IC is ready for ASIL B or ASIL D levels projects with its Securyzr integrated Secure Element